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| Title | A Hardware Architecture Of Nist Lightweight Cryptography Applied In Ipsec To Secure High-Throughput Low-Latency Iot Networks |
|---|---|
| ID_Doc | 2011 |
| Authors | Tran S.-N.; Hoang V.-T.; Bui D.-H. |
| Year | 2023 |
| Published | IEEE Access, 11 |
| DOI | http://dx.doi.org/10.1109/ACCESS.2023.3306420 |
| Abstract | The Internet of Things (IoT) has rapidly grown in recent years, making it an integral part of many areas of our lives. Many IoT networks require high data throughput and low latency, allowing for real-time communication and data transmission, enabling improved efficiency, cost savings, and enhanced decision-making capabilities in various industries such as manufacturing, healthcare, transportation, and smart cities. However, with the increasing amount of data being transmitted, the security of high-speed IoT networks becomes a critical concern. In this paper, we proposed a hardware architecture for Ascon, a NIST Lightweight cryptography standard to enable high-throughput, low-latency security services in IPSec protocols. Results show that the ESP protocol can achieve a maximum throughput of 8.806 Gbps and a minimum latency of 427ns for only 2812 Slice. This ESP core together with the proposed Ascon implementation can be used in IoT gateways to provide security services for high-speed, low-latency IoT networks. © 2013 IEEE. |
| Author Keywords | Ascon; Internet of Things; IPSec; lightweight cryptography |
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